Microelectronic devices are fabricated on a semiconductor substrate as integrated circuits in which various conductive layers are interconnected with one another to permit electronic signals to propagate within the device. An example of such a device is a complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) or MOSFET.
An exemplary FET or MOSFET includes a gate electrode on a gate dielectric layer on a surface of a silicon substrate. Source/drain regions are provided along opposite sides of the gate electrode. The source and drain regions are heavily doped regions of the silicon substrate. Usually a silicide layer, for example, nickel silicide is used to couple contacts in an interlayer dielectric to the source and drain regions.
The contact resistance associated to the silicide/silicon interface is one of the biggest challenges to solve in order to preserve drive current capabilities. The required contact resistivity of ultra-thin silicide on silicon source/drain of the transistor beyond the 22 nm node needs to be below 4×10−9 ohm-cm2. However, nickel silicide (NiSi), currently the most widely accepted alloy, has a contact resistivity on the order of 1×10−8 ohm-cm2.
Different contact schemes have been developed to achieve low effective Schottky barrier height (SBH) between metal and silicon source/drain diffusion regions. One such method involves inserting an interfacial oxide between metal and silicon to reduce the density of metal-induced gap states (MIGS). Another method involves SBH tuning by interfacial SiO2 or high-K dielectric induced dipoles. However, insertion of a high bandgap oxide with a large conduction band offset results in large tunnel resistivity and would offset the positive effect of Fermi unpinning.
Thus, there is a need for new contact schemes that provide contact resistivities below 1×10−8 ohm-cm2.